1. Field of the Invention
The present invention relates to a method for manufacturing an SOI (Silicon-On-Insulator) wafer having a high degree of flatness when bonded and an epitaxial silicon wafer, and a method for manufacturing a silicon wafer serving as a support substrate for these wafers.
2. Description of the Related Art
A highly integrated CMOS (Complementary Metal Oxide Semiconductor), an IC, a high-withstand voltage device, and others have been conventionally fabricated by utilizing an SOI wafer. The SOI wafer in which a single-crystal silicon layer used as a device forming region is formed on an insulating layer is effective for prevention of latch-up (an abnormal oscillation phenomenon due to a parasitic circuit) in case of a highly integrated circuit and insulative isolation from a base substrate in case of a high-withstand voltage device. As a method for manufacturing this SOI wafer, a method of bonding silicon wafers to each other through a silicon dioxide layer, i.e., an insulating layer is known, an SOI wafer fabricated by this bonding method has very excellent crystallinity of an SOI layer, and hence this method appears promising.
However, since the insulating layer formed of the silicon oxide layer has a smaller thermal expansion coefficient than single-crystal silicon, there is an inconvenience. For example, the SOI layer side warps into a convex shape and an adsorption error occurs in a device process when an oxide film is not formed on a backside surface of a support substrate.
In order to eliminate this problem, there have been proposed method for manufacturing an SOI wafer heating both wafers to a predetermined temperature to be bonded to each other, then performing a thermal oxidation processing with respect to these wafers to form an oxide film on an entire surface thereof, polishing a surface of one wafer which is preferably a wafer having an oxide film formed thereon before bonding, and reducing a thickness of this wafer, thereby obtaining a bonded wafer (see, e.g., Japanese Patent Application Laid-open No. 250615-1991 (claims)).
Further, in an epitaxial silicon wafer having an epitaxial layer grown on an epitaxial growth silicon wafer formed of silicon single crystal, it is known that warpage occurs when a resistivity value in the epitaxial growth silicon wafer is different from a resistivity value in the epitaxial layer. That is because elastic deformation due to misfit in grating constant between the epitaxial layer and the epitaxial growth silicon wafer as a substrate occurs.
In order to solve this problem, there has been proposed a method for manufacturing an epitaxial silicon wafer identifying irregularities in a warped shape of an epitaxial growth silicon wafer, estimating warpage that occurs when an epitaxial layer is formed on a surface of this wafer, and forming the epitaxial layer on the concave surface of the epitaxial growth silicon wafer (see, e.g., Japanese Patent Application Laid-open No. 112120-1994 (claims)). According to this method for manufacturing, warpage of the surface of the epitaxial growth silicon wafer is identified in advance, a direction of this warpage is set to a direction opposite to a direction of a warping change that occurs in epitaxial growth, and the warping change in epitaxial growth is thereby canceled out, thus reducing an absolute value of warpage of the epitaxial silicon wafer.
However, the SOI wafer avoids warpage by providing the oxide film on upper and lower surfaces of a support substrate silicon wafer thereof. Therefore, presence of the oxide film on the lower surface of the SOI wafer is necessarily the premise for avoiding warpage, but the oxide film present on the lower surface of the SOI wafer may be removed in a subsequent device process in some cases. This SOI wafer still has a problem to be solved. Namely, when the oxide film on the lower surface is removed in the device process, unevenness in thermal shrinkage amounts on the upper and lower surfaces of the support substrate silicon wafer occurs, and the SOI wafer newly warps in the device process.
Further, in the epitaxial silicon wafer, when an ingot formed of a silicon single crystal is sliced into a thin discoid shape by using, e.g., an inner diameter slicer or a wire saw device, warpage can be given to the wafer in advance. On the other hand there is an inconvenience that an amount of warpage is relatively large and becomes uneven in a moving direction perpendicular to a moving direction of the inner diameter slicer or a traveling direction of a wire for slicing the ingot. Moreover, there is still a problem to be solved. That is, obtaining a flat epitaxial silicon wafer is difficult even if an epitaxial layer is formed on a surface of the epitaxial growth silicon wafer having such uneven warpage.
It is an object of the present invention to provide a method for manufacturing a silicon wafer, which can obtain an SOI wafer or an epitaxial silicon wafer having a high degree of flatness.